1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device, in which a current flowing through a memory cell is compared with a current flowing through a reference cell, to read storage data of the memory cell based on a result of comparison. More particularly, the invention relates to a structure for accurately reading the storage data of a memory cell in a nonvolatile semiconductor memory device.
2. Description of the Background Art
For reducing power consumption and heating, power supply voltages have been lowered in semiconductor integrated circuit devices. Likewise, power supply voltages have been lowered in semiconductor memory devices. In a nonvolatile semiconductor memory device, which is one kind of such semiconductor memory devices, memory cell data is read through the use of a sense amplifier (current sense amplifier) of a current sense type. The current sense amplifier includes a current mirror stage supplying a constant current, and compares a drive current of a selected memory cell with a drive current of a reference cell. The current sense amplifier produces internal data based on a result of this comparison, and thus, the data of the selected memory cell is read out.
In the current sense amplifier, transistors forming the current mirror stage must operate in a saturation region for accurately performing the sensing operation. In the saturation region, a MOS transistor (insulated gate field effect transistor) must satisfy the following relation:Vds≧Vgs−Vth, where Vds represents a drain-source voltage, Vgs represents a gate-source voltage, and Vth represents a threshold voltage.
If the current mirror stage of the sense amplifier is formed of P-channel MOS transistors, a power supply voltage is supplied to a source, and a voltage corresponding to the comparison result occurs at a drain. As is seen from the above relation, when the power supply voltage is low, MOS transistor is extremely difficult to operate in the saturation region for performing a sensing operation with high accuracy.
P-channel MOS transistor has a gate electrode, which is usually formed of polycrystalline silicon doped with N-type impurities, and the P-channel MOS transistor has a threshold voltage of a large absolute value due to a difference in work function between the gate electrode and a semiconductor substrate. The N-type gate electrode attracts electrons toward a surface of the semiconductor substrate, and works against formation of an inversion layer when a channel is formed. For decreasing the absolute value of the threshold voltage of the P-channel MOS transistor, P-type impurities are implanted into the substrate surface. Therefore, the channel is formed at an inside deeper than the surface of the semiconductor substrate. Such MOS transistor is referred to as a buried channel MOS transistor.
The buried channel is a region doped with impurities of the same conductivity type as the source and drain regions. In the buried channel MOS transistor, since carriers (holes) pass through an inside region of the substrate, mobility is large so that subthreshold characteristics deteriorate when the absolute value of the threshold voltage lowers, resulting in an increased leakage current. Therefore, it is difficult to implement a lower threshold voltage, and the P-channel MOS transistor requires a gate-source voltage of a certain magnitude to be made conductive, and is difficult to operate on a lower supply voltage, as compared to an N-channel MOS transistor. Therefore, when a P-channel MOS transistor is employed in the current mirror stage of a current sense amplifier, such a problem arises that an accurate sensing operation cannot be precisely achieved under a low power supply voltage condition.
A construction for performing the sensing operation with high precision is disclosed in a prior art reference 1 (Japanese Patent Laying-Open No. 4-216397). In the construction disclosed in the prior art reference 1, a sense circuit is configured of a differential amplifier and an offset circuit, and currents of different magnitudes are supplied to a normal bit line of a memory cell array and a reference bit line connected to a reference cell. The prior art reference 1 intends to improve static and dynamic characteristics of a sense amplifier of a current offset type by supplying the offset current.
In such semiconductor memory devices, different amounts of a current flow through a memory cell depending on an operation temperature. For accurately reading memory cell data, it is necessary to read the data by sensing the memory cell current while compensating such temperature characteristics.
A prior art reference 2 (World Patent Publication No. 2003-530656) discloses a construction for compensating for such temperature dependency of the memory cell current due to the difference in operation temperature. This prior art reference 2 discloses a construction for effecting temperature compensation on a word line voltage in an Automatic Program Disturbance Erasure Verify (APDEV) operation of verifying that a leakage current of a predetermined value or greater does not flow through a bit line in a program (write and erase) operation.
A prior art reference 3 (Japanese Patent Laying-Open No. 2003-217287) discloses a construction for compensating for temperature dependency of a memory cell current. In the prior art reference 3, the temperature dependency of the memory cell current is canceled by controlling temperature dependency of a word line voltage and temperature dependency of a discharging time of a bit line, to achieve a threshold voltage distribution of small temperature dependency among memory cells.
A further construction for reducing the temperature dependency of the threshold voltage distribution of the memory cells is disclosed in a prior art reference 4 (Japanese Patent Laying-Open No. 2001-35177). The prior art reference 4 employs a current source generating a temperature-dependent current and a current source producing a constant current independent of a temperature, and adjusts the temperature characteristics in both positive and negative directions by selectively using these current sources.
In the construction disclosed in the prior art reference 1, imbalanced currents are supplied to a normal bit line connected to normal memory cells and a reference bit line connected to reference cells, so that characteristics similar to those of a sense circuit of a load-imbalance type may be achieved to eliminate a restriction on the power supply voltage of the sense circuit of the load-imbalanced type.
In the construction disclosed in the prior art reference 1, however, imbalanced currents are always supplied to the normal bit line and the reference bit line, and it is difficult to supply a load current to only one of the normal and reference bit lines for verifying memory cell characteristics.
The construction disclosed in the prior art 2 utilizes the fact that temperature dependency of a resistance value is different between a P-type resistance element and an N-type resistance element, and is configured to combine selectively the P- and N-type resistance elements for producing a predetermined gradient in the resistance value depending on an operation temperature, to implement temperature compensation of the voltage applied to a word line. In the construction disclosed in the prior art reference 2, it is necessary to adjust adaptively the combination of the P- and N-type resistance elements according to the temperature, to make the temperature control difficult.
In the construction disclosed in the prior art reference 3, a temperature-dependent word line voltage is employed for canceling the temperature dependency of the memory cell current. In the prior art reference 3, however, no consideration is given to the case where the temperature dependency of characteristics is different between the normal memory cell and the reference memory cell.
The construction disclosed in the prior art reference 4 likewise makes the word line voltage temperature-dependent so as to cancel the temperature dependency of the memory cell current, for compensating for temperature dependency of the memory cell currents. In this prior art reference 4, however, no consideration is given to the case where the temperature dependency of the drive current is different between the normal memory cell and the reference memory cell.
Further, in the prior art references 1 to 4, no consideration is given to the configuration and sensing operation of the sense amplifier for achieving a highly precise sensing of memory cell current even under a low power supply voltage condition.